UDR. has been granted a patent for an apparatus featuring a host board with multiple connectors for unique compute devices. The system allows a compute device to access first firmware during a power-on cycle, while blocking access to its own firmware, enabling coordinated operation with other devices. GlobalData’s report on UDR gives a 360-degree view of the company including its patenting strategy. Buy the report here.
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According to GlobalData’s company profile on UDR, was a key innovation area identified from patents. UDR's grant share as of July 2024 was 69%. Grant share is based on the ratio of number of grants to total number of patents.
Apparatus for firmware access during compute device connection
The patent US12056245B1 describes a non-transitory processor-readable medium containing instructions that facilitate the operation of a first compute device when connected to a host board. The process begins with the interruption of the power-on cycle of the first compute device upon its connection to the host board, which stores a specific firmware. Following this interruption, the first compute device accesses the first firmware from the host board and resumes its power-on cycle using this firmware. The claims further detail the collaborative operation of the first compute device with a second compute device, which is also connected to the host board, allowing both devices to function collectively as an enhanced overall compute device with capabilities exceeding those of each device individually.
Additionally, the patent outlines various operational scenarios, including the role of a management circuit on the host board that coordinates the operation of both compute devices based on user input. The instructions also encompass validation checks to ensure proper access to the firmware, which is uniquely associated with the respective types of compute devices. The host board can manage multiple compute devices and firmware types, enabling a flexible and efficient computing environment. The claims emphasize the potential for increased functionality and performance when multiple devices are interconnected, highlighting the advantages of this system in a shared computing architecture.
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